Visible Photon Counter OEM | SIMTRUM Photonics Store

Parameters

Min

Typical

Max

Units

Wavelength Range

350

900

nm

Active area diameter

ID101-20 / ID101-SMF20

20

μm

ID101-50 / ID101-MMF50 or MMFF100

50

μm

Timing resolution [FWHM]*

40

60

ps

Single-photon detection probability (SPDE)**

at 400nm

15

18

%

at 500nm

30

35

%

at 600nm

20

25

%

at 700nm

15

18

%

at 800nm

5

7

%

at 900nm

3

4

%

Dark count rate (DCR)

ID101-20

30

250

Hz

ID101-50

100

300

Hz

Afterpulsing probability*

0.5

%

Output pulse width

ID101-20 / ID101-SMF20**

30

35

40

ns

ID101-50 / ID101-MMF50 or MMFF100**

40

45

50

ns

Output pulse amplitude (in high impedance)**

VDD

V

Output driver capability

4

mA

Deadtime

ID101-20 / ID101-SMF20

30

35

40

ns

ID101-50 / ID101-MMF50 or MMFF100

40

45

50

ns

Maximum count rate (pulsed light)

ID101-20 / ID101-SMF20*

28

MHz

ID101-50 / ID101-MMF50 or MMFF100*

22

MHz

VDD supply voltage

4.8

5.0

5.2

V

Current on VDD

0.25

2.2

mA

VOP supply voltage

-24

-26

V

Current on VOP

100

μA

Storage Temperature

-40

70

°C

Many industrial applications would greatly benefit from a single-photon detector array. When the required array size is reasonably small (i.e. < 10x10), it is possible to assemble several closely spaced TO5 headers to form an array. As illustrated in the figure, opposite, for a 3x3 array, several TO headers can be mounted on a printed circuit board. The minimum center-to-center pitch is 9.5 mm. Common electronic circuits for power supply, output stage and temperature control can be implemented on the PCB. If a high accuracy for the distance from pixel to pixel is required or if a large array is needed, IDQ offers a custom design service for the design of an application-specific CMOS chip.

Power Stage 

The ID101 requires two power supplies, VDD and VOP. A standard inverting DC/DC converter can convert the +5V level to the high negative voltage level VOP. The remaining electronic circuits on the PCB board can be supplied with the same +5 V power. Two 100 nF capacitances must be added as close as possible to the output pins for decoupling purpose. 

Output Stage 

The ID101 output can be shaped for the back-end electronic circuits (e.g. counter, TDC, TAC) using the circuit shown below. A D-type Flip-Flop with asynchroneous clear combined with a delay generator (RC for instance) and an inverter with a Schmitt trigger input allows to set the pulse width and the dead time. 

Temperature Control 

For proper operation, it is highly recommended to implement a thermal stabilisation circuit on the final printed circuit board, using the single-stage TEC and the 2.2 kΩ thermistor provided. Integrated temperature controllers for Peltier modules are commercially available.

Timing Tagging Devices

Ultra-fast Pulse Generator for TCSPC

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